ICS601-01
L
OW
P
HASE
N
OISE
C
LOCK
M
ULTIPLIER
Description
The ICS601-01 is a low-cost, low phase noise,
high-performance clock synthesizer for applications
which require low phase noise and low jitter. It is ICS’
lowest phase noise multiplier, and also the lowest
CMOS part in the industry. Using ICS’ patented
analong and digital Phase-Locked Loop (PLL)
techniques, the chip accepts a 10 - 27 MHz crystal or
clock input, and produces output clocks up to 156 MHz
at 3.3 V.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input
and output skew and jitter are not defined nor
guaranteed. For applications which require definted
input to output timing, use the ICS670-01.
Features
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Packaged in 16-pin SOIC or TSSOP
Available in Pb (lead) free package
Uses fundamental 10 - 27 MHz crystal or clock
Patented PLL with the lowest phase noise
Output clocks up to 156 MHz at 3.3 V
Low phase noise: -132 dBc/Hz at 10 kHz
Low jitter - 18 ps one sigma typ.
Full swing CMOS outputs with 25 mA drive capability
at TTL levels
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Advanced, low power, sub-micron CMOS process
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Industrial temperature range available
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Operating voltage of 3.3V or 5V
Block Diagram
VDD
3
Reference
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
CLK
X1/ICLK
Crystal or
clock input
Crystal
Oscillator
X2
ROM Based
Multipliers
REFOUT
VCO
Divide
4
S3:0
3
GND
OE
REFEN
MDS 601-01 L
I n t e gra te d C i r c u i t S y s t e m s
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1
525 Race Stre et, San Jo se, CA 9 5126
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Revision 111204
te l (40 8) 2 97-12 01
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w w w. i c st . c o m
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
