PRELIMINARY INFORMATION
ICS650-21
System Peripheral Clock Source
Minimum
Typical
Maximum
7
VDD+0.5
70
260
150
5.5
0.8
0.4
50
30
±50
5
25.000
Units
V
V
C
C
C
V
V
V
V
V
V
mA
mA
mA
pF
MHz
ppm
ns
ns
%
%
ps
ps
ps
Electrical Specifications
Parameter
Supply voltage, VDD
Inputs and Clock Outputs
Ambient Operating Temperature
Soldering Temperature
Storage temperature
Operating Voltage, VDD
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Voltage, VOH, VDD = 3.3 or 5V
Operating Supply Current, IDD, at 5V
Operating Supply Current, IDD, at 3.3V
Short Circuit Current, VDD = 3.3
Input Capacitance
Input Crystal or Clock Frequency
Output Clocks Accuracy (synthesis error)
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle, UCLCK
Output Clock Duty Cycle, PCLCK, ACLCK
One Sigma Jitter, except ACLK
One Sigma Jitter, ACLK
Absolute Clock Period Jitter PCLK, UCLK, 20M
Conditions
Referenced to GND
Referenced to GND
Max of 10 seconds
ABSOLUTE MAXIMUM RATINGS (note 1)
-0.5
0
-65
3.0
2
DC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)
Select inputs, OE
Select inputs, OE
VDD=3.3V, IOH=-8mA
2.4
VDD=3.3V, IOL=8mA
IOH=-8mA
VDD-0.4
No Load, note 2
No Load, note 2
Each output
Except X1
AC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)
All clocks
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
At VDD/2
1
1.5
1.5
60
55
40
45
50
50
75
120
- 500
500
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. With all clocks at highest frequencies.
External Components
The ICS650 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.1µF should be connected between VDD and GND (on pins 4 and 6, and pins 16 and 14),
as close to the chip as possible. A series termination resistor of 33Ω may be used for each clock output. The
25.000 MHz crystal must be connected as close to the chip as possible. The crystal should be a fundamental
mode, parallel resonant, 30ppm or better (to meet the Ethernet specs). Crystal capacitors should be
connected from pins X1 to ground and X2 to ground. The value of these capacitors is given by the
following equation, where C
L
is the crystal load capacitance: Crystal caps (pF) = (C
L
-12) x 2. So for a
crystal with 16pF load capacitance, two 8pF caps should be used. If a clock input is used, drive it into X1
and leave X2 unconnected.
MDS 650-21 A
3
Revision 010301
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
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