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ICS650R-11I 参数 Datasheet PDF下载

ICS650R-11I图片预览
型号: ICS650R-11I
PDF下载: 下载PDF文件 查看货源
内容描述: 博通网络时钟合成器 [BroadCom Networking Clock Synthesizer]
分类和应用: 时钟
文件页数/大小: 4 页 / 66 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
 浏览型号ICS650R-11I的Datasheet PDF文件第1页浏览型号ICS650R-11I的Datasheet PDF文件第2页浏览型号ICS650R-11I的Datasheet PDF文件第4页  
ICS650-11B  
BroadCom Networking Clock Synthesizer  
Electrical Specifications  
Parameter  
Conditions  
Minimum  
Typical  
Maximum Units  
ABSOLUTE MAXIMUM RATINGS (note 1)  
Supply voltage, VDD  
Referenced to GND  
7
VDD+0.5  
85  
V
V
Inputs and Clock Outputs  
Ambient Operating Temperature  
Soldering Temperature  
Storage temperature  
Referenced to GND  
Max of 20 seconds  
-0.5  
-40  
°C  
°C  
°C  
260  
-65  
150  
DC CHARACTERISTICS (VDD = 3.3V unless noted)  
Operating Voltage, VDD  
3
5.5  
V
V
Input High Voltage, VIH, X1 pin only  
Input Low Voltage, VIL, X1 pin only  
VDD/2 + 1  
VDD/2  
VDD/2 VDD/2 - 1  
V
Output High Voltage, VOH  
Output Low Voltage, VOL  
IOH=-12mA  
IOL=12mA  
IOH=-8mA  
No Load  
2.4  
V
0.4  
V
Output High Voltage, VOH, CMOS level  
Operating Supply Current, IDD  
Short Circuit Current  
VDD-0.4  
V
35  
mA  
mA  
Each output  
±50  
AC CHARACTERISTICS (VDD = 3.3V unless noted)  
Input Frequency  
25.000  
1.5  
MH z  
ns  
Output Clock Rise Time  
Output Clock Fall Time  
Output Clock Duty Cycle, except 25 MHz  
Frequency error  
0.8 to 2.0V  
2.0 to 0.8V  
1.5  
ns  
At VDD/2  
45  
50  
55  
0
%
All clocks  
ppm  
ps  
Absolute Jitter, short term  
Variation from mean  
175  
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged  
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.  
External Components  
The ICS650-11B requires a minimum number of external components for proper operation. Decoupling  
capacitors of 0.01µF should be connected between each VDD and GND on Pins 4 and 6, and Pins 16 and  
14, as close to the ICS650-11B as possible. A series termination resistor of 33 may be used for each clock  
output. The 25.00 MHz crystal must be connected as close to the chip as possible. The crystal should be a  
fundamental mode (do not use third overtone), parallel resonant. Crystal capacitors should be connected  
from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these capacitors is  
given by the following equation, where C is the crystal load capacitance: Crystal caps (pF) = (C -6) x 2. So  
L
L
for a crystal with 16 pF load capacitance, two 20 pF caps should be used.  
MDS 650-11B C  
3
Revision 012005  
Printed 11/14/04  
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel• www.icst.com