ICS670-01
Low Phase Noise Zero Delay Buffer and Multiplier
300
200
100
(ps)
CL = 20 pF
0
0
-100
-200
-300
-400
CLK2 Frequency (MHz)
25
50
75
100
125
150
Skew
CL = 10 pF
Figure 1.
ICS670-01 skew from ICLK to CLK2, with change in load capacitance.
VDD = 3.3 V.
Adjusting Input/Output Skew
The data in Figure 1 can be used to adjust individual circuit characteristics and achieve the minimum
possible skew between ICLK and CLK2. With a 125 MHz output, for example, having a total load
capacitance of 15 pF will result in nearly zero skew between ICLK and CLK2. Note that the load
capacitance includes board trace capacitance, input capacitance of the load being driven by the ICS670-01,
and any additional capacitors connected to CLK2.
0
-20
Phase Noise (dBc/Hz)
-40
-60
-80
-100
-120
-140
10.0E+0
100.0E+0
1.0E+3
10.0E+3
100.0E+3
1.0E+6
10.0E+6
Offset from Carrier (Hz)
Figure 2.
Phase Noise of ICS670-01 at 125 MHz out, 25 MHz clock input.
VDD = 3.3 V.
4
Revision 100900
Printed 11/15/00
Integrated Circuit Systems • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel•http://www.icst.com
MDS 670-01 B
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
