ICS670-02
L
OW
P
HASE
N
OISE
, Z
ERO
D
ELAY
B
UFFER AND
M
ULTIPLIER
Description
The ICS670-02 is a high speed, low phase noise, Zero
Delay Buffer (ZDB) which integrates ICS’ proprietary
analog/digital Phase Locked Loop (PLL) techniques.
Part of ICS’ ClockBlocks
TM
family, the part’s zero delay
feature means that the rising edge of the input clock
aligns with the rising edges of the outputs giving the
appearance of no delay through the device. There are
two identical outputs on the chip. The FBCLK should be
used to connect to the FBIN. Each output has its own
output enable pin.
The ICS670-02 is ideal for synchronizing outputs in a
large variety of systems, from personal computers to
data communications to video. By allowing off-chip
feedback paths, the chip can eliminate the delay
through other devices. The 15 different on-chip
multipliers work in a variety of applications. For other
multipliers, including functional multipliers, see the
ICS527.
Features
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Packaged in 16-pin SOIC
Available in Pb (lead) free package
Clock inputs from 5 to 160 MHz (see page 2)
Patented PLL with low phase noise
Output clocks up to 160 MHz at 3.3 V
15 selectable on-chip multipliers
Power down mode available
Low phase noise: -111 dBc/Hz at 10 kHz
Output enable function tri-states outputs
Low jitter 15 ps one sigma
Advanced, low power, sub-micron CMOS process
Operating voltage of 3.3 V or 5 V
Block Diagram
VDD
3
OE1
IC L K
F B IN
Divide by
N
Phase
Detector,
Charge
Pump, and
Loop Filter
Voltage
Controlled
Oscillator
FBCLK
S 3 :S 0
4
CLK2
3
GND
E x te rn a l F e e d b a c k fro m F B C L K is re c o m m e n d e d .
OE2
MDS 670-02 F
In te grated Circui t Systems
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1
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ICS [ INTEGRATED CIRCUIT SYSTEMS ]
