ICS7152A
Spread Spectrum Clock Generator
External Components
The ICS7152A requires a minimum number of external
components for proper operation.
away from the ICS7152A. This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between GND and VDD on pins 3 and 6, as close to
these pins as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
Crystal Information
The crystal used should be a fundamental mode,
parallel resonant. Crystal capacitors should be
connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value of these
capacitors is given by the following equation:
Crystal caps (pF) = (C
L
- 6) x 2
In the equation, C
L
is the crystal load capacitance. So,
for a crystal with a 16 pF load capacitance, two 20 pF
[(16-6) x 2] capacitors should be used.
Series Termination Resistor
Series termination should be used on the clock output.
To series terminate a 50Ω trace (a commonly used
trace impedance) place a 27Ω resistor in series with
the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
25Ω.
Spread Spectrum Profile
The ICS7152A low EMI clock generator uses a
triangular frequency modulation profile for optimal
down stream tracking of zero delay buffers and other
PLL devices. The frequency modulation amplitude is
constant with variations of the input frequency.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
the decoupling capacitor and VDD pin. The PCB trace
to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via.
2) To minimize EMI, the 27Ω series termination resistor
(if needed) should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
Modulation Rate
Frequency
Time
MDS 7152A A
Integrated Circuit Systems, Inc.
●
3
525 Race Street, San Jose, CA 95126
●
Revision 102005
tel (408) 297-1201
●
www.icst.com
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