Integrated
Circuit
Systems, Inc.
ICS83052I
2:1, S
INGLE
-E
NDED
M
ULTIPLEXER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3, 6
4
5
7
8
Name
V
DDO
GND
CLK1, CLK0
V
DD
OE
SEL0
Q
Power
Power
Input
Power
Input
Input
Output
Type
Description
Output supply pin.
Power supply ground.
Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.
Core supply pin.
Output enable. When LOW, outputs are in HIGH impedance state.
Pullup
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
Clock select input. See Control Input Function Table.
Pulldown
LVCMOS / LVTTL interface levels.
Single-ended clock output. LVCMOS/LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
V
DDO
= 3.465V
V
DDO
= 2.625V
V
DDO
= 1.89V
Test Conditions
Minimum
Typical
4
51
51
18
19
19
15
Maximum
Units
pF
kΩ
kΩ
pF
pF
pF
Ω
T
ABLE
3. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Control Inputs
SEL0
0
1
Input Selected to Q
CLK0
CLK1
83052AGI
www.icst.com/products/hiperclocks.html
2
REV. A AUGUST 2, 2005
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
