Integrated
Circuit
Systems, Inc.
ICS83840
DDR SDRAM MUX
F
EATURES
•
40 low skew single-ended DIMM ports
•
4 SSTL-2 compatible enable inputs
•
Maximum Switching Speed: 3ns
•
Output skew: 120ps (maximum)
•
Bank skew: 45ps (maximum)
•
r
on
= 8Ω (typical)
•
Full 2.5V supply modes
•
0°C to 70°C ambient operating temperature
•
Pin compatible with the CBTV4010
G
ENERAL
D
ESCRIPTION
The ICS83840 is a DDR SDRAM MUX and is
a member of the HiPerClock S™ family of High
HiPerClockS™
Performance Clock Solutions from ICS. The
device has 10 Host Lines and each host line can
be passed to 4 Data Ports. The 10 channels are
allocated as follows in the DDR SDRAM application: 8 data
lines, 1 strobe line and 1 DQm line. The Host/Data Ports are
compatible with single-ended SSTL-2 and the device oper-
ates from a 2.5V supply.
ICS
Guaranteed low output skew makes the ICS83840 ideal for
demanding applications which require well defined perfor-
mance and repeatability.
S
IMPLIFIED
S
CHEMATIC
L
OGIC
D
IAGRAM
HP0
R
ON
Sw
Sw
Sw
0DP0
1DP0
2DP0
Sw
3DP0
HPx
nDPx
400Ω
HP9
R
ON
Sw
Sw
Sw
Sw
0DP9
1DP9
2DP9
3DP9
nSn
SW
nS0
nS1
nS2
P
IN
A
SSIGNMENT
1
A
B
C
D
E
F
G
H
J
K
L
2DP 9
1DP9
0DP9
1DP8
0DP8
3DP7
V
DD
nS2
nc
nS3
4
GND
2
nS 1
V
DD
nS3
GND
3DP9
HP9
3DP8
2DP8
HP8
GND
2DP7
3
nc
nS0
5
1DP0
0DP0
6
2DP0
HP0
7
3DP0
0DP1
8
1DP1
9
2DP1
HP1
10
3DP1
GND
HP 2
3DP2
0DP3
HP 3
GND
0DP4
HP 4
11
0DP2
1DP2
2DP2
1DP3
2DP3
3DP3
1DP4
2DP4
0DP5
REV. A DECEMBER 22, 2003
ICS83840
64-Ball TFBGA
7mm x 7mm x 1.2mm
package body
H Package
Top View
HP 7
1DP7
0DP7
3DP6
2DP6
HP6
1DP6
GND
0DP6
3DP5
HP5
2DP5
3DP4
1DP5
83840AH
www.icst.com/products/hiperclocks.html
1
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
