Integrated
Circuit
Systems, Inc.
ICS83841
20 B
IT
, DDR SDRAM 2:1 MUX
F
EATURES
•
Forty low skew single-ended DIMM ports
•
One SSTL-2 compatible select input
•
Maximum Switching Speed: 3ns
•
Output skew: 180ps (maximum)
•
r
on
= 20Ω (typical)
•
Full 2.5V supply modes
•
0°C to 70°C ambient operating temperature
•
Available in both standard and lead-free RoHS compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS83841 is a 20 Bit, DDR SDRAM 2:1 MUX
and is a member of the HiPerClockS™ family of
HiPerClockS™
High Performance Clock Solutions from ICS. The
device has 20 host lines and each host line can
be passed to 2 data ports. The host/data ports
are compatible with single-ended SSTL-2 and the device op-
erates from a 2.5V supply.
IC
S
Guaranteed low output skew makes the ICS83841 ideal for
demanding applications which require well defined performance
and repeatability.
S
IMPLIFIED
S
CHEMATIC
L
OGIC
D
IAGRAM
DH0
r
on
Sw
Sw
DA0
DB0
DHx
DAx or DBx
R
PD
DH19
r
on
Sw
Sw
DA19
DB19
S
S
SW
P
IN
A
SSIGNMENT
1
A
B
C
D
E
F
G
H
J
K
DB
17
DA
18
DB
18
DA
19
DB
19
DA
0
DB
0
DA
1
DB
1
DA
2
2
DA
17
DH
17
DH
18
GND
DH
19
DH
0
GND
DH
1
DH
2
DB
2
3
DB
16
DH
16
4
DB
15
DA
16
5
DA
15
DH
15
GND
6
DB
14
DH
14
GN D
7
DA
14
DB
13
8
DA
13
DH
13
9
DB
12
DH
12
DH
11
GN D
10
DA
12
DB
11
DA
11
DB
10
DA
10
DB
9
DA
9
DB
8
DA
8
DB
7
REV. A JANUARY 20, 2006
ICS83841
72-Ball TFBGA
6mm x 6mm x 1.2mm
package body
H Package
Top View
S
V
DD
GND
DH
3
DA
3
DB
3
DA
4
DH
4
DB
4
GN D
DH
5
DA
5
DA
6
DB
5
V
DD
V
DD
DH
10
DH
9
GN D
DH
8
DH
6
DB
6
DH
7
DA
7
83841BH
www.icst.com/products/hiperclocks.html
1
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
