Integrated
Circuit
Systems, Inc.
ICS8305I
L
OW
S
KEW
, 1-
TO
-4, M
ULTIPLEXED
D
IFFERENTIAL
/
LVCMOS-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
Type
Power
Input
Power
Input
Input
Input
Input
Input
Output
Power
Description
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 9, 13
2
3
4
5
6
7
8
10, 12, 14, 16
11, 15
Name
GND
OE
V
DD
CLK_EN
CL K
nCLK
CLK_SEL
LVCMOS_CLK
Q3, Q2, Q1, Q0
V
DDO
Power supply ground.
Output enable. When LOW, outputs are in HIGH impedance state.
Pullup
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
Core supply pin.
Synchronizing clock enable. When LOW, the output clocks are
Pullup
disabled. When HIGH, output clocks are enabled.
LVCMOS / LVTTL interface levels.
Pulldown Non-inver ting differential clock input.
Pullup/
Inver ting differential clock input. V
DD
/2 default when left floating.
Pulldown
Clock select input. When HIGH, selects CLK, nCLK inputs.
Pullup
When LOW, selects LVCMOS_CLK input.
LVCMOS / LVTTL interface levels.
Pulldown LVCMOS / LVTTL clock input.
Clock outputs. LVCMOS / LVTTL interface levels.
Output supply pins.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
Test Conditions
Minimum
Typical
4
51
51
11
5
7
12
Maximum
Units
pF
kΩ
kΩ
pF
Ω
8305AGI
www.icst.com/products/hiperclocks.html
2
REV. B MAY 19, 2005
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
