Integrated
Circuit
Systems, Inc.
ICS83948I-01
L
OW
S
KEW
, 1-
TO
-12
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
F
EATURES
•
12 LVCMOS outputs
•
Selectable LVCMOS clock or differential CLK, nCLK inputs
•
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
LVCMOS_CLK accepts the following input levels:
LVCMOS or LVTTL
•
Maximum output frequency: 150MHz
•
Output skew: 350ps (maximum)
•
Part to part skew: 1.5ns (maximum)
•
3.3V core, 3.3V output
•
-40°C to 85°C ambient operating temperature
•
Pin compatible with the MPC948/948L
G
ENERAL
D
ESCRIPTION
The ICS83948I-01 is a low skew, 1-to-12 Differ-
ential-to-LVCMOS Fanout Buffer and a member
HiPerClockS™
of the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS83948I-01 has
two selectable clock inputs. The CLK, nCLK pair
can accept most standard differential input levels. The
LVCMOS_CLK can accept LVCMOS or LVTTL input levels.
The low impedance LVCMOS outputs are designed to drive
50Ω series or parallel terminated transmission lines. The
effective fanout can be increased from 12 to 24 by utilizing
the ability of the outputs to drive two series terminated lines.
,&6
The ICS83948I-01 is characterized at 3.3V core/3.3V output.
Guaranteed output and part-to-part skew characteristics make
the ICS83948I-01 ideal for those clock distribution applications
demanding well defined performance and repeatability.
B
LOCK
D
IAGRAM
CLK_EN
D
Q
LVCMOS_CLK
CLK
nCLK
1
Q0
0
Q1
CLK_SEL
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
OE
P
IN
A
SSIGNMENT
GND
GND
V
DDO
V
DDO
Q0
Q1
Q2
Q3
32 31 30 29 28 27 26 25
CLK_SEL
LVCMOS_CLK
CLK
nCLK
CLK_EN
OE
V
DD
GND
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Q11
V
DDO
Q10
GND
Q9
V
DDO
Q8
GND
24
23
22
GND
Q4
V
DDO
Q5
GND
Q6
V
DDO
Q7
ICS83948I-01
21
20
19
18
17
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
83948AYI-01
www.icst.com/products/hiperclocks.html
1
REV. A SEPTEMBER 23, 2002
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
