Integrated
Circuit
Systems, Inc.
ICS8431-21
350MH
Z
, L
OW
J
ITTER
, C
RYSTAL
O
SCILLATOR
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
F
EATURES
•
Fully integrated PLL
•
Differential 3.3V LVPECL output
•
Crystal oscillator interface
•
Output frequency range: 62.5MHz to 350MHz
•
Crystal input frequency range: 14MHz to 25MHz
•
VCO range: 250MHz to 700MHz
•
Programmable PLL loop divider for generating a variety
of output frequencies
•
Spread Spectrum Clocking (SSC) fixed at 1/2% modulation
for environments requiring ultra low EMI
•
PLL bypass modes supporting in-circuit testing and on-chip
functional block characterization
•
Cycle-to-cycle jitter: 30ps (maximum)
•
3.3V supply voltage
•
0°C to 85°C ambient operating temperature
•
Replaces ICS8431-01 and ICS8431-11
•
Lead-Free package fully RoHS compliant
G
ENERAL
D
ESCRIPTION
The ICS8431-21 is a general purpose clock fre-
ICS
quency synthesizer for IA64/32 application and a
HiPerClockS™
member of the HiPerClockS™ family of High Per-
formance Clock Solutions from ICS. The VCO op-
erates at a frequency range of 250MHz to 700MHz
providing an output frequency range of 62.5MHz to 350MHz.
The output frequency can be programmed using the parallel in-
terface, M0 through M8 to the configuration logic, and the output
divider control pin, DIV_SEL. Spread spectrum clocking is pro-
grammed via the control inputs SSC_CTL0 and SSC_CTL1.
Programmable features of the ICS8431-21 support four op-
erational modes. The four modes are spread spectrum clock-
ing (SSC), non-spread spectrum clock and two test modes
which are controlled by the SSC_CTL[1:0] pins. Unlike other
synthesizers, the ICS8431-21 can immediately change
spread-spectrum operation without having to reset the device.
In SSC mode, the output clock is modulated in order to achieve
a reduction in EMI. In one of the PLL bypass test modes, the
PLL is disconnected as the source to the differential output
allowing an external source to be connected to the TEST_I/O
pin. This is useful for in-circuit testing and allows the differen-
tial output to be driven at a lower frequency throughout the
system clock tree. In the other PLL bypass mode, the oscilla-
tor divider is used as the source to both the M and the Fout
divide by 2. This is useful for characterizing the oscillator and
internal dividers.
B
LOCK
D
IAGRAM
XTAL_IN
OSC
XTAL_OUT
÷
16
P
IN
A
SSIGNMENT
M0
M1
M2
M3
M4
M5
M6
M7
M8
SSC_CTL0
SSC_CTL1
V
EE
TEST_I/O
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
nP_LOAD
V
CC
XTAL_IN
XTAL_OUT
nc
nc
V
CCA
V
EE
MR
DIV_SEL
V
CCO
FOUT
nFOUT
V
EE
PLL
PHASE
DETECTOR
÷2
VCO
÷
M
÷4
FOUT
nFOUT
ICS8431-21
TEST_I/O
Configuration
Logic
SSC
Control
Logic
M0:M8
28-Lead SOIC
7.5mm x 18.05mm x 2.25mm package body
M Package
Top View
nP_LOAD
SSC_CTL0
SSC_CTL1
DIV_SEL
8431AM-21
www.icst.com/products/hiperclocks.html
1
REV. A APRIL 27, 2005