Integrated
Circuit
Systems, Inc.
ICS8431-21
350MH
Z
, L
OW
J
ITTER
, C
RYSTAL
O
SCILLATOR
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
A
PPLICATION
I
NFORMATION
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8431-21 provides
separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. V
CC
, V
CCA
, and V
CCO
should
be individually connected to the power supply plane through
vias, and bypass capacitors should be used for each pin. To
achieve optimum jitter performance, better power supply iso-
lation is required.
Figure 3
illustrates how a 10Ω along with a
10μF and a .01μF bypass capacitor should be connected to
each V
CCA
pin.
3.3V
V
CC
.01μF
V
CCA
.01μF
10μF
10Ω
F
IGURE
3. P
OWER
S
UPPLY
F
ILTERING
T
ERMINATION
FOR
LVPECL O
UTPUTS
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 2A and 2B
show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
The clock layout topology shown below is typical for
IA64/32 platforms. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Z
o
= 50Ω
FOUT
FIN
125Ω
Z
o
= 50Ω
FOUT
125Ω
Z
o
= 50Ω
50Ω
1
Z
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
o
50Ω
V
CC
- 2V
RTT
FIN
Z
o
= 50Ω
84Ω
84Ω
RTT =
F
IGURE
2A. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
2B. LVPECL O
UTPUT
T
ERMINATION
8431AM-21
www.icst.com/products/hiperclocks.html
8
REV. A APRIL 27, 2005
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
