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ICS8430AY-51 参数 Datasheet PDF下载

ICS8430AY-51图片预览
型号: ICS8430AY-51
PDF下载: 下载PDF文件 查看货源
内容描述: 600MHZ ,低抖动LVCMOS / LVTTL - TO- 3.3V LVPECL频率合成器 [600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER]
分类和应用:
文件页数/大小: 16 页 / 149 K
品牌: ICS [ INTEGRATED CIRCUIT SYSTEMS ]
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PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-51
600MH
Z
, L
OW
J
ITTER
LVCMOS/ LVTTL-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
F
EATURES
Dual differential 3.3V LVPECL outputs
Selectable crystal oscillator interface
or LVCMOS/LVTTL TEST_CLK
Maximum output frequency: 600MHz
Crystal input frequency range: 14MHz to 25MHz
VCO range: 200MHz to 700MHz
Parallel or serial interface for programming counter
and output dividers
RMS period jitter: 2.6ps (typical)
Cycle-to-cycle jitter: 17ps (typical)
3.3V supply voltage
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
G
ENERAL
D
ESCRIPTION
The ICS8430-51 is a general purpose, dual output
Crystal-to-3.3V Differential LVPECL High Frequency
HiPerClockS™
Synthesizer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS8430-51 has a selectable TEST_CLK
or crystal inputs. The VCO operates at a frequency range of
200MHz to 700MHz. With FOUT0 configured to divide the
VCO frequency by 2, output frequency steps as small as
2MHz can be achieved using a 16MHz crystal or reference clock.
FOUT1 provides an additional divide by 16 and 180° phase shift.
Output frequencies up to 600MHz can be programmed using
the serial or parallel interfaces to the configuration logic. The low
jitter and frequency range of the ICS8430-51 make it an ideal
clock generator for most clock tree applications.
,&6
B
LOCK
D
IAGRAM
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL1
OSC
XTAL2
÷
16
1
P
IN
A
SSIGNMENT
VCO_SEL
nP_LOAD
XTAL2
M4
M3
M2
M1
M0
32 31 30 29 28 27 26 25
0
M5
M6
M7
M8
N0
N1
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
TEST
V
CC
FOUT1
nFOUT1
V
CCO
FOUT0
nFOUT0
V
EE
24
23
22
XTAL1
TEST_CLK
XTAL_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
ICS8430-51
21
20
19
18
17
PLL
PHASE DETECTOR
MR
÷
M
÷
2
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N2
CONFIGURATION
INTERFACE
LOGIC
VCO
0
÷
N
1
÷16
N2
V
EE
FOUT0
nFOUT0
FOUT1
nFOUT1
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8430AY-51
www.icst.com/products/hiperclocks.html
1
REV. D FEBRUARY 11, 2003