Integrated
Circuit
Systems, Inc.
ICS8521I-03
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
F
EATURES
•
9 LVHSTL outputs
•
Redundant differential CLK0, nCLK0 and CLK1, nCLK1 inputs
•
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
•
Maximum output frequency: 500MHz
•
Output skew: 50ps (maximum)
•
Part-to-part skew: 250ps (maximum)
•
Propagation delay: 1.6ns (maximum)
•
V
OH
= 1V (maximum)
•
3.3V core, 1.8V output operating supply voltages
•
-40°C to 85°C ambient operating temperature
G
ENERAL
D
ESCRIPTION
The ICS8521I-03 is a low skew, 1-to-9 Differen-
tial-to-LVHSTL Fanout Buffer and a member of
HiPerClockS™
the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS8521I-03 has
two selectable clock inputs. Redundant clock
pairs, CLK0, nCLK0 and CLK1, nCLK1 can accept most stan-
dard differential input levels. The clock enable is internally syn-
chronized to eliminate runt pulses on the outputs during asyn-
chronous assertion/deassertion of the clock enable pin.
,&6
Guaranteed output skew and part-to-part skew characteris-
tics make the ICS8521I-03 ideal for today’s most advanced
applications, such as IA64 and static RAMs.
B
LOCK
D
IAGRAM
CLK_EN
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
D
Q
LE
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
P
IN
A
SSIGNMENT
V
DDO
nQ2
Q2
nQ1
Q1
nQ0
Q0
V
DDO
32 31 30 29 28 27 26 25
V
DD
CLK0
nCLK0
CLK_SEL
CLK1
nCLK1
GND
CLK_EN
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9 1 0 1 1 1 2 1 3 1 4 1 5 16
V
DDO
Q6
nQ6
Q7
nQ7
Q8
nQ8
V
DDO
V
DDO
Q3
nQ3
Q4
nQ4
Q5
nQ5
V
DDO
ICS8521I-03
32-Lead LQFP
7mm x 7mm x 1.4mm Package Body
Y Package
Top View
8521AYI-03
www.icst.com/products/hiperclocks.html
1
REV. A APRIL 29, 2003
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
