Integrated
Circuit
Systems, Inc.
ICS8521
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
F
EATURES
•
9 LVHSTL outputs
•
Selectable CLK, nCLK or LVPECL clock inputs
•
CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
•
Maximum output frequency up to 500MHz
•
Output skew: 50ps (maximum)
•
Part-to-part skew: 250ps (maximum)
•
Propagation delay: 1.8ns (maximum)
•
V
OH
= 1.2V (maximum)
•
3.3V core, 1.8V output operating supply voltages
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
G
ENERAL
D
ESCRIPTION
The ICS8521 is a low skew, 1-to-9 3.3V Differ-
ential-to-LVHSTL Fanout Buffer and a member of
HiPerClockS™
the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS8521 has two
selectable clock inputs. The CLK, nCLK pair can
accept most standard differential input levels. The PCLK,
nPCLK pair can accept LVPECL, CML, or SSTL input levels.
The clock enable is internally synchronized to eliminate runt
pulseson the outputs during asynchronous assertion/
deassertion of the clock enable pin.
,&6
Guaranteed output skew, part-to-part skew and crossover
voltage characteristics make the ICS8521 ideal for today’s
most advanced applications, such as IA64 and static RAMs.
B
LOCK
D
IAGRAM
CLK_EN
CLK
nCLK
PCLK
nPCLK
CLK_SEL
D
Q
LE
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
P
IN
A
SSIGNMENT
V
DDO
nQ2
Q2
nQ1
Q1
nQ0
Q0
V
DDO
32 31 30 29 28 27 26 25
V
DD
CLK
nCLK
CLK_SEL
PCLK
nPCLK
GND
CLK_EN
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9 1 0 1 1 1 2 1 3 1 4 1 5 16
V
DDO
Q6
nQ6
Q7
nQ7
Q8
nQ8
V
DDO
V
DDO
Q3
nQ3
Q4
nQ4
Q5
nQ5
V
DDO
ICS8521
32-Lead LQFP
7mm x 7mm x 1.4mm Package Body
Y Package
Top View
8521BY
www.icst.com/products/hiperclocks.html
1
REV. B JULY 31, 2001
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
