Integrated
Circuit
Systems, Inc.
ICS8523
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
F
EATURES
•
4 differential 1.8V LVHSTL outputs
•
Selectable CLK, nCLK or LVPECL clock inputs
•
CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
•
Maximum output frequency up to 650MHz
•
Translates any single-ended input signal to 1.8V LVHSTL
levels with resistor bias on nCLK input
•
Output skew: 30ps (maximum)
•
Part-to-part skew: 150ps (maximum)
•
Propagation delay: 1.6ns (maximum)
•
3.3V core, 1.8V output operating supply
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
G
ENERAL
D
ESCRIPTION
The ICS8523 is a low skew, high perfor-
mance 1-to-4 Differential-to-LVHSTL fanout buffer
HiPerClockS™
and a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8523 has two selectable clock inputs. The
CLK, nCLK pair can accept most standard differential input
levels. The PCLK, nPCLK pair can accept LVPECL, CML, or
SSTL input levels. The clock enable is internally synchronized
to eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
,&6
Guaranteed output and part-to-part skew characteristics
make the ICS8523 ideal for those applications demanding
well defined performance and repeatability.
B
LOCK
D
IAGRAM
CLK_EN
D
Q
LE
CLK
nCLK
PCLK
nPCLK
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
P
IN
A
SSIGNMENT
GND
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
nc
nc
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V
DDO
Q1
nQ1
Q2
nQ2
V
DDO
Q3
nQ3
CLK_SEL
ICS8523
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm body package
G Package
Top View
8523BG
www.icst.com/products/hiperclocks.html
1
REV. B JULY 31, 2001