Integrated
Circuit
Systems, Inc.
ICS853014
L
OW
S
KEW
, 1-
TO
-5
2.5V/3.3V D
IFFERENTIAL
-
TO
-LVPECL/ECL F
ANOUT
B
UFFER
A
PPLICATION
I
NFORMATION
W
IRING THE
D
IFFERENTIAL
I
NPUT TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
Figure 2
shows an example of the differential input that can be
wired to accept single ended levels. The reference voltage level
V
BB
generated from the device is connected to the negative input.
The C1 capacitor should be located as close as possible to the
input pin.
VDD(or VCC)
CLK_IN
+
VBB
-
C1
0.1uF
F
IGURE
2. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
T
ERMINATION
FOR
3.3V LVPECL O
UTPUTS
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 3A and 3B
show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
3.3V
Z
o
= 50Ω
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
125Ω
FOUT
FIN
125Ω
Z
o
= 50Ω
FOUT
FIN
Z
o
= 50Ω
50Ω
1
Z
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
o
50Ω
V
CC
- 2V
RTT
Z
o
= 50Ω
84Ω
84Ω
RTT =
F
IGURE
3A. LVPECL O
UTPUT
T
ERMINATION
853014BG
F
IGURE
3B. LVPECL O
UTPUT
T
ERMINATION
REV. C MAY 13, 2005
www.icst.com/products/hiperclocks.html
8
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
