Integrated
Circuit
Systems, Inc.
ICS8530-01
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
F
EATURES
•
16 differential 3.3V LVPECL outputs
•
CLK, nCLK input pair
•
CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Maximum output frequency up to 500MHz
•
Translates any single-ended input signal to 3.3V LVPECL
levels with a resistor bias on nCLK input
•
Output skew: 75ps (maximum)
•
Part-to-part skew: 250ps (maximum)
•
3.3V output operating supply
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
G
ENERAL
D
ESCRIPTION
The ICS8530-01 is a low skew, 1-to-16 Differen-
tial-to-3.3V LVPECL Fanout Buffer and a mem-
HiPerClockS™
ber of the HiPerClockS™ family of High Perfor-
mance Clock Solutions from ICS. The CLK, nCLK
pair can accept most standard differential input
levels. The high gain differential amplifier accepts peak-to-
peak input voltages as small as 150mV as long as the com-
mon mode voltage is within the specified minimum and maxi-
mum range.
,&6
Guaranteed output and part-to-part skew characteristics
make the ICS8530-01 ideal for those clock distribution appli-
cations demanding well defined performance and repeatabil-
ity.
B
LOCK
D
IAGRAM
CLK
nCLK
P
IN
A
SSIGNMENT
nCLK
V
CCO
Q15
nQ15
Q14
nQ14
V
EE
Q13
nQ13
Q12
nQ12
V
CCO
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q15
nQ15
Q14
nQ14
Q13
nQ13
Q12
nQ12
Q11
nQ11
Q10
nQ10
Q9
nQ9
Q8
nQ8
V
CCO
Q11
nQ11
Q10
nQ10
V
EE
Q9
nQ9
Q8
nQ8
V
CCO
V
CC
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
ICS8530-01
CLK
V
CCO
nQ0
Q0
nQ1
Q1
V
EE
nQ2
Q2
nQ3
Q3
Vcco
48-Pin LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8530DY-01
www.icst.com/products/hiperclocks.html
1
V
CCO
nQ4
Q4
nQ5
Q5
V
EE
nQ6
Q6
nQ7
Q7
V
CCO
V
CC
REV. B AUGUST 8, 2001
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
