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ICS85357AG-01 参数 Datasheet PDF下载

ICS85357AG-01图片预览
型号: ICS85357AG-01
PDF下载: 下载PDF文件 查看货源
内容描述: 4 :1或2 : 1差分至3.3V LVPECL / ECL时钟多路复用器 [4:1 OR 2:1 DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER]
分类和应用: 复用器时钟
文件页数/大小: 12 页 / 122 K
品牌: ICS [ INTEGRATED CIRCUIT SYSTEMS ]
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Integrated
Circuit
Systems, Inc.
ICS85357-01
4:1
OR
2:1
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
M
ULTIPLEXER
F
EATURES
High speed differential multiplexer. The device can be
configured as either a 4:1 or 2:1 multiplexer
1 differential 3.3V LVPECL output
4 selectable CLK, nCLK inputs
CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency up to 750MHz
Translates any single ended input signal to 3.3V LVPECL
levels with resistor bias on nCLKx input
Part-to-part skew: 150ps (maximum)
Propagation delay: 1.5ns (maximum)
LVPECL mode operating voltage supply range:
V
CC
= 3.135V to 3.465V, V
EE
= 0V
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3.135V to -3.465V
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
G
ENERAL
D
ESCRIPTION
The ICS85357-01 is a 4:1 or 2:1 Differential-to-
3.3V LVPECL / ECL clock multiplexer which can
HiPerClockS™
operate up to 750MHz and is a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS85357-01 has 4
selectable clock inputs. The CLK, nCLK pair can accept most
standard differential input levels. The device can operate
using a 3.3V LVPECL (V
EE
= 0V, V
CC
= 3.135V to 3.465V) or
3.3V ECL (V
CC
= 0V, V
EE
= -3.135V to -3.465V). The fully dif-
ferential architecture and low propagation delay make it
ideal for use in clock distribution circuits. The select pins have
internal pulldown resistors. Leaving one input unconnected
(pulled to logic low by the internal resistor) will transform
the device into a 2:1 multiplexer. The SEL1 pin is the most
significant bit and the binary number applied to the select pins
will select the same numbered data input (i.e., 00
selects CLK0, nCLK0).
,&6
B
LOCK
D
IAGRAM
CLK0
nCLK0
CLK1
nCLK1
CLK2
nCLK2
CLK3
nCLK3
00
P
IN
A
SSIGNMENT
V
CC
CLK0
nCLK0
CLK1
nCLK1
CLK2
nCLK2
CLK3
nCLK3
V
EE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
SEL1
SEL0
V
CC
Q0
nQ0
V
CC
nc
nc
V
EE
01
Q0
nQ0
10
11
ICS85357-01
SEL1 SEL0
20-Lead TSSOP
4.40mm x 6.50mm x 0.90mm body package
G Package
Top View
85357AG-01
www.icst.com/products/hiperclocks.html
1
REV. A JULY 16, 2001