Integrated
Circuit
Systems, Inc.
ICS85408
L
OW
S
KEW
, 1-
TO
-8
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
D
ISTRIBUTION
C
HIP
F
EATURES
•
8 Differential LVDS outputs
•
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
•
Maximum output frequency: 700MHz
•
Translates any differential input signal (LVPECL, LVHSTL,
SSTL, HCSL) to LVDS levels without external bias networks
•
Translates any single-ended input signal to LVDS with
resistor bias on nCLK input
•
Multiple output enable inputs for disabling unused outputs
in reduced fanout applications
•
Output skew: 50ps (maximum)
•
Part-to-part skew: 550ps (maximum)
•
Propagation delay: 2.4ns (maximum)
•
3.3V operating supply
•
0°C to 70°C ambient operating temperature
•
Lead-Free package RoHS compliant
G
ENERAL
D
ESCRIPTION
The ICS85408 is a low skew, high performance
1-to-8 Differential-to-LVDS Clock Distribution
HiPerClockS™
Chip and a member of the HiPerClock ™
S
family of High Performance Clock Solutions
from ICS. The ICS85408 CLK, nCLK pair can ac-
cept most differential input levels and translates them to 3.3V
LVDS output levels. Utilizing Low Voltage Differential
Signaling (LVDS), the ICS85408 provides a low power, low
noise, low skew, point-to-point solution for distributing LVDS
clock signals.
ICS
Guaranteed output and part-to-part skew specifications make
the ICS85408 ideal for those applications demanding well
defined performance and repeatability.
B
LOCK
D
IAGRAM
OE
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
P
IN
A
SSIGNMENT
nQ6
Q6
nQ5
Q5
nQ4
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Q7
nQ7
OE
GND
V
DD
V
DD
GND
V
DD
CLK
nCLK
Q0
nQ0
CLK
nCLK
ICS85408
24-Lead, 173-MIL TSSOP
4.4mm x 7.8mm x 0.92mm body package
G Package
Top View
85408BG
www.icst.com/products/hiperclocks.html
1
REV. A APRIL 25, 2005
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
