PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8543
L
OW
S
KEW
, 1-
TO
-4
LVDS F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- G S
UFFIX
N
c
20
11
L
E1
E
1
10
α
D
A2
A
-C-
e
b
A1
SEATING
PLANE
aaa C
T
ABLE
6. P
ACKAGE
D
IMENSIONS
SYMBOL
MIN
N
A
A1
A2
b
c
D
E
E1
e
L
α
aaa
0.45
0°
--
4.30
--
0.05
0.80
0.19
0.09
6.40
6.40 BASIC
4.50
0.65 BASIC
0.75
8°
0.10
1.20
0.15
1.05
0.30
0.20
6.60
Millimeters
MAX
20
--
0.002
0.032
0.007
0.0035
0.252
0.047
0.006
0.041
0.012
0.008
0.260
MIN
Inches
MAX
0.252 BASIC
0.169
0.177
0.0256 BASIC
0.018
0°
--
0.030
8°
0.004
Reference Document: JEDEC Publication 95, MO-153
ICS8543BG
www.icst.com/products/hiperclocks.html
6
REV. C MAY 21, 2001