Integrated
Circuit
Systems, Inc.
L
OW
S
KEW
¸1, ¸2
C
LOCK
G
ENERATOR
F
EATURES
20 LVCMOS outputs, 7Ω typical output impedance
Output frequency up to 250 MHz
150ps bank skew, 200ps output, 250ps multiple frequency
skew, 650ps part-to-part skew
Translates any differential input signal (PECL, HSTL, LVDS)
to LVCMOS levels without external bias networks
Translates any single-ended input signal to LVCMOS levels
with a resistor bias on nCLK input
Translates any single-ended input signal to inverted LVCMOS
levels with a resistor bias on CLK input
LVCMOS / LVTTL control inputs
Bank enable logic allows unused banks to be disabled
in reduced fanout applications
3.3V or mixed 3.3V input, 2.5V output operating
supply modes
48 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm
package body, 0.5mm package lead pitch
0°C to 70°C ambient operating temperature
Other divide values available on request
ICS8702
The ICS8702 is a very low skew,
÷1, ÷2
Clock
Generator and a member of the HiPerClockS
HiPerClockS™
family of High Performance Clock Solutions
from ICS. The ICS8702 is designed to trans-
late any differential signal levels to LVCMOS lev-
els. True or inverting, single-ended to LVCMOS translation
can be achieved with a resistor bias on the nCLK or CLK
inputs, respectively. The effective fanout can be increased
from 20 to 40 by utilizing the ability of the outputs to drive two
series terminated lines.
G
ENERAL
D
ESCRIPTION
,&6
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The bank enable
inputs, BANK_EN0:1, supports enabling and disabling each
bank of outputs individually. The master reset input, nMR/OE,
resets the internal frequency dividers and also controls the
enabling and disabling of all outputs simultaneously.
The ICS8702 is characterized at 3.3V and mixed 3.3V input
supply, and 2.5V output supply operating modes. Guaranteed
bank, output, multiple frequency and part-to-part skew char-
acteristics make the ICS8702 ideal for those clock distribu-
tion applications demanding well defined performance and
repeatability.
B
LOCK
D
IAGRAM
CLK
nCLK
DIV_SELA
1
0
÷1
÷2
1
0
P
IN
A
SSIGNMENT
GND
QB2
GND
QB3
VDDO
QB4
QC0
VDDO
QC1
GND
QC2
GND
QAO - QA4
QC3
VDDO
QC4
QD0
VDDO
QD1
GND
QD2
GND
QD3
VDDO
QD4
QB0 - QB4
DIV_SELB
1
0
QC0 - QC4
DIV_SELC
1
0
QD0 - QD4
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
ICS8702
QB1
VDDO
QB0
QA4
VDD0
QA3
GND
QA2
GND
QA1
VDDO
QA0
DIV_SELA
DIV_SELB
CLK
nCLK
VDDI
BANK_EN0
GND
BANK_EN1
VDDI
nMR/OE
DIV_SELC
DIV_SELD
DIV_SELD
nMR/OE
BANK_EN0
BANK_EN1
Bank Enable
Logic
48-Lead LQFP
Y Package
Top View
8702
www.icst.com
1
REV. A - AUGUST 7, 2000
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
