Integrated
Circuit
Systems, Inc.
ICS87993I
1-
TO
-5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
PLL C
LOCK
D
RIVER W
/D
YNAMIC
C
LOCK
S
WITCH
F
EATURES
•
5 differential 3.3V LVPECL outputs
•
Selectable differential clock inputs
•
CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
•
VCO range: 200MHz to 500MHz
•
External feedback for “zero delay” clock regeneration
with configurable frequencies
•
Cycle-to-cycle jitter (RMS): 20ps (maximum)
•
Output skew: 70ps (maximum), within one bank
•
3.3V supply voltage
•
-40°C to 85°C ambient operating temperature
•
Pin compatible with MPC993
G
ENERAL
D
ESCRIPTION
The ICS87993I is a PLL clock driver designed
specifically for redundant clock tree designs. The
HiPerClockS™
device receives two differential LVPECL clock
signals from which it generates 5 new differen-
tial LVPECL clock outputs. Two of the output pairs
regenerate the input signal frequency and phase while the
other three pairs generate 2x, phase aligned clock outputs.
External PLL feedback is used to also provide zero delay
buffer performance.
,&6
The ICS87993I Dynamic Clock Switch (DCS) circuit continu-
ously monitors both input CLK signals. Upon detection of a
failure (CLK stuck HIGH or LOW for at least 1 period), the
INP_BAD for that CLK will be latched (H). If that CLK is the
primary clock, the DCS will switch to the good secondary
clock and phase/frequency alignment will occur with minimal
output phase disturbance. The typical phase bump caused
by a failed clock is eliminated.
P
IN
A
SSIGNMENT
nQB0
nQB1
nQB2
QB0
QB1
QB2
V
CC
24 23 22 21 20 19 18 17
nQA1
QA1
nQA0
QA0
V
CC
V
CCA
MAN_OVERRIDE
PLL_SEL
25
26
27
28
29
30
31
32
1
nMR
V
CC
16
V
CC
INP0BAD
INP1BAD
CLK_SELECTED
V
EE
nEXT_FB
EXT_FB
V
EE
ICS87993I
32-Lead QFP (LQFP)
7mm x 7mm x 1.4mm
package body
Y Package
Top View
2
nALARM_RESET
15
14
13
12
11
10
9
3
CLK0
4
nCLK0
5
CLK_SEL
6
CLK1
7
nCLK1
8
V
EE
B
LOCK
D
IAGRAM
PLL_SEL
CLK_SELECTED
INP1BAD
INP0BAD
MAN_OVERRIDE
ALARM_RESET
SEL_CLK
nCLK0
CLK0
nCLK1
CLK1
nEXT_FB
EXT_FB
nMR
87993AYI
Dynamic Switch
Logic
nQB0
QB0
nQB1
QB1
÷2
PLL
÷4
nQB2
QB2
nQA0
QA0
nQA1
QA1
www.icst.com/products/hiperclocks.html
1
REV. B May 21, 2003
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
