Integrated
Circuit
Systems, Inc.
ICS932S422C
PCIe Gen 2 main Clock for Intel-based Servers
Recommended Application:
PCIe Gen 2 & FBD compliant CK410B/CK410B+ clock for
Intel-based servers
Output Features:
•
5 - 0.7V current-mode differential CPU pairs
•
4 - 0.7V current-mode differential SRC pair
•
4 - PCI (33MHz)
•
3 - PCICLK_F, (33MHz) free-running
•
1 - 48MHz
•
2 - REF, 14.318MHz
Key Specifications:
•
CPU cycle-cycle jitter: < 50ps
•
SRC cycle-cycle jitter: < 125ps
•
PCI cycle-cycle jitter: < 500ps
•
CPU output skew: < 100ps
•
SRC output skew: < 250ps
•
± 300ppm frequency accuracy on all outputs except
48MHz
•
± 100ppm frequency accuracy on 48MHz
Features/Benefits:
•
Supports spread spectrum modulation, 0 to -0.5%
down spread
•
•
•
•
Uses external 14.318MHz crystal and external load
capacitors for low ppm synthesis error
CPU clocks independent of SRC/PCI clocks
D2/D3 SMBus address
Compliant with PCIe Gen II phase noise specifications
Functionality
FSLC
0
0
0
0
1
1
1
1
1
Pin Configuration
2
FSLB
0
0
1
1
0
0
1
1
1
FSLA
0
1
0
1
0
1
0
1
CPU
MHz
266.67
133.33
200.00
166.67
333.33
100.00
400.00
SRC
MHz
100.00
100.00
100.00
100.00
100.00
100.00
100.00
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
Reserved
REF
MHz
14.318
14.318
14.318
14.318
14.318
14.318
14.318
U
SB
MHz
48.000
48.000
48.000
48.000
48.000
48.000
48.000
56-pin SSOP & TSSOP
1412A—12/10/07
ICS932S422
1. FSLB and FSLC are three-level inputs. Please see VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for
correct values. Also refer to the Test Clarification Table.
2.FSLA is a low-threshold input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
VDDPCI
GNDPCI
PCICLK0
PCICLK1
PCICLK2
PCICLK3
GNDPCI
VDDPCI
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDD48
48MHz
GND48
VDDSRC
NC
Vtt_PwrGd#/PD
SRCCLKC1
SRCCLKT1
GNDSRC
SRCCLKT2
SRCCLKC2
SRCCLKC3
SRCCLKT3
VDDSRC
SRCCLKT4
SRCCLKC4
VDDSRC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
FSLC/TEST_SEL
REF0
REF1
VDDREF
X1
X2
GNDREF
FSLB/TEST_MODE
FSLA
VDDCPU
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GNDCPU
CPUCLKT2
CPUCLKC2
VDDCPU
CPUCLKT3
CPUCLKC3
VDDA
GNDA
IREF
CPUCLKT4
CPUCLKC4
SDATA
SCLK
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