Product Data Sheet
M2020/21
VCSO B
ASED
C
LOCK
PLL
G
ENERAL
D
ESCRIPTION
The M2020/21 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for optical network systems
supporting 2.5-10 GB data rates.
It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M2020/21 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
F
EATURES
◆
Integrated SAW (surface acoustic wave) delay line;
low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz
or 50kHz to 80MHz)
◆
Output frequencies of 15 to 700 MHz
*
◆
LVPECL clock output (CML and LVDS options available)
◆
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
◆
Loss of Lock (LOL) output pin
◆
Narrow Bandwidth control input (NBW pin)
◆
Hitless Switching (HS) options with or without Phase
Build-out (PBO) available for SONET (GR-253) /
SDH (G.813) MTIE and TDEV compliance during
reference clock reselection
◆
Industrial temperature grade available
◆
Single 3.3V power supply
◆
Small 9 x 9 mm SMT (surface mount) package
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using
M2020-11-622.0800 or M2021-11-622.0800
Input Reference
Clock
(MHz)
(M2020)
(M2021)
PLL Ratio
(Pin Selectable)
(M2020)
(M2021)
Output Clock
(MHz)
19.44 or 38.88
77.76
155.52
622.08
32 or 16
8
4
1
622.08
Table 1: Example I/O Clock Frequency Combinations
* Specify VCSO center frequency at time of order.
S
IMPLIFIED
B
LOCK
D
IAGRAM
Loop
Filter
NBW
LOL
MR_SEL1:0
FIN_SEL1:0
P_SEL2:0
Figure 2: Simplified Block Diagram
M2020/21 Datasheet Rev 1.0
M2020/21 VCSO Based Clock PLL
Revised 30Jul2004
●
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
●
●
tel (508) 852-5400
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
