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MK3727DTR 参数 Datasheet PDF下载

MK3727DTR图片预览
型号: MK3727DTR
PDF下载: 下载PDF文件 查看货源
内容描述: LOW COST 24 - 36 MHZ 3.3伏VCXO [LOW COST 24 - 36 MHZ 3.3 VOLT VCXO]
分类和应用: 晶体外围集成电路石英晶振压控振荡器光电二极管时钟
文件页数/大小: 6 页 / 78 K
品牌: ICS [ INTEGRATED CIRCUIT SYSTEMS ]
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MK3727
L
OW
C
OST
24 - 36 MH
Z
3.3 V
OLT
VCXO
External Component Selection
The MK3727 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD (pin 2) and GND (pin 4), as close to
these pins as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the MK3727. There should be no via’s between
the crystal pins and the X1 and X2 device pins. There
should be no signal traces underneath or close to the
crystal.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors
on the PCB is optional. The need for these capacitors
is determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture
and frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
To determine the need for and value of the crystal
adjustment capacitors, you will need a PC board of
your final layout, a frequency counter capable of about
1 ppm resolution and accuracy, two power supplies,
and some samples of the crystals which you plan to
use in production, along with measured initial accuracy
for each crystal at the specified crystal load
capacitance, CL.
To determine the value of the crystal capacitors:
1. Connect VDD of the MK3727 to 3.3V. Connect pin 3
of the MK3727 to the second power supply. Adjust the
voltage on pin 3 to 0V. Measure and record the
frequency of the CLK output.
2. Adjust the voltage on pin 3 to 3.3V. Measure and
record the frequency of the same output.
To calculate the centering error:
Series Termination Resistor
When the PCB trace between the clock output (CLK,
pin 5) and the load is over 1 inch, series termination
should be used. To series terminate a 50Ω trace (a
commonly used trace impedance) place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
Quartz Crystal
The MK3727 VCXO function consists of the external
crystal and the integrated VCXO oscillator circuit. To
assure the best system performance (frequency pull
range) and reliability, a crystal device with the
recommended parameters (shown below) must be
used, and the layout guidelines discussed in the
following section shown must be followed.
The frequency of oscillation of a quartz crystal is
determined by its “cut” and by the load capacitors
connected to it. The MK3727 incorporates on-chip
variable load capacitors that “pull” (change) the
frequency of the crystal. The crystal specified for use
with the MK3727 is designed to have zero frequency
error when the total of on-chip + stray capacitance is
14pF.
Recommended Crystal Parameters:
Initial Accuracy at 25
°
C
Temperature Stability
Aging
Load Capacitance
Shunt Capacitance, C0
C0/C1 Ratio
Equivalent Series Resistance
6
(
f
3.0V
f
t arg et
)
+
(
f
0V
f
t arg et
)
Error = 10 x ------------------------------------------------------------------------------
error
xtal
f
t arg et
Where:
±20 ppm
±30 ppm
±20 ppm
14 pf
7 pF Max
250 Max
35
Max
f
target
= nominal crystal frequency
error
xtal
=actual initial accuracy (in ppm) of the crystal
being measured
If the centering error is less than ±25 ppm, no
adjustment is needed. If the centering error is more
than 25ppm negative, the PC board has excessive
stray capacitance and a new PCB layout should be
MDS 3727 E
Int egrat ed C ircuit Syste ms
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3
525 R ace S tr eet, San Jose, CA 95126
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Revision 052901
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