Philips Semiconductors
Product data sheet
Hot swappable I
2
C and SMBus bus buffer
PCA9513; PCA9514
DESCRIPTION
The PCA9513 and PCA9514 are hot swappable I
2
C and SMBus
buffers that allows I/O card insertion into a live backplane without
corrupting the data and clock buses. Control circuitry prevents the
backplane from being connected to the card until a stop command
or bus idle occurs on the backplane without bus contention on the
card. When the connection is made, the PCA9511, PCA9513, and
PCA9514 provides bi-directional buffering, keeping the backplane
and card capacitances isolated.
Rise time accelerator circuitry allows the use of weaker DC pull-up
currents while still meeting rise time requirements. The PCA9513
and PCA9514 incorporate a digital ENABLE input pin, which
enables the device when asserted HIGH and forces the device into
a low current mode when asserted LOW, and an open-drain READY
output pin, which indicates that the backplane and card sides are
connected together (HIGH) or not (LOW).
The PCA9513 supplies a 92
µA
current source to SCLIN and SDAIN
in lieu of using pull-up resistors for PICMG backplane applications.
Including the current source in the device provides for a consistent
RC time constant as cards are removed and inserted into the
backplane. The current source is high-impedance whenever the pin
voltage is greater than the part V
CC
.
PCA9513 and PCA9514 rise time accelerator threshold is 0.8 V to
provide improved noise margin over the PCA9510 and PCA9511.
The dynamic offset design of the PCA9510/11/12/13/14 I/O drivers
allow them to be connected to another PCA9510/11/12/13/14 device
in series or in parallel and to the A side of the PCA9517. The
PCA9510/11/12/13/14 can
not
connect to the static offset I/Os used
on the PCA9515/15A/16/16A/17 B side and PCA9518.
FEATURES
•
Bi-directional buffer for SDA and SCL lines increases fanout and
prevents SDA and SCL corruption during live board insertion and
removal from multi-point backplane systems
•
Compatible with I
2
C standard mode, I
2
C fast mode, and SMBus
standards
•
∆V/∆t
rise time accelerators on all SDA and SCL lines
•
Rise time accelerator threshold moved from 0.6 V to 0.8 V for
improved noise margin
•
Active HIGH ENABLE input
•
Active HIGH READY open-drain output
•
High-impedance SDA and SCL pins for V
CC
= 0 V
•
92
µA
current source on SCLIN and SDAIN for PICMG backplane
applications (PCA9513 only)
•
Supports clock stretching and multiple master
arbitration/synchronization
APPLICATION
•
cPCI, VME, AdvancedTCA cards and other multi-point backplane
cards that are required to be inserted or removed from an
operating system.
•
Operating power supply voltage range: 2.7 V to 5.5 V
•
5.5 V tolerant I/Os
•
0 kHz to 400 kHz clock frequency
•
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115, and 1000 V CDM per
JESD22-C101
•
Latch-up testing is done to JEDEC Standard JESD78 which
•
Packages offered: SO8, TSSOP8 (MSOP8)
ORDERING INFORMATION
PACKAGES
8-pin plastic SO
8-pin plastic SO
8-pin plastic TSSOP (MSOP)
8-pin plastic TSSOP (MSOP)
TEMPERATURE RANGE
–40
°C
to +85
°C
–40
°C
to +85
°C
–40
°C
to +85
°C
–40
°C
to +85
°C
ORDER CODE
PCA9513D
PCA9514D
PCA9513DP
PCA9514DP
TOPSIDE MARK
PCA9513
PCA9514
9513
9514
DRAWING NUMBER
SOT96-1
SOT96-1
SOT505-1
SOT505-1
exceeds 100 mA
Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.
2004 Oct 05
2
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
