V103A
T
RIPLE
10-B
IT
LVDS T
RANSMITTER FOR
V
IDEO
General Description
The V103A LVDS display interface transmitter is
primarily designed to support pixel data transmission
between a video processing engine and a digital video
display. The data rate supports up to SXGA+
resolutions and can be used in Plasma, Rear Projector,
Front Projector, CRT and LCD display applications. It
can also be used in other high-bandwidth parallel data
applications and provides a low EMI interconnect over
a low cost, low bus width cable up to several meters in
length.
The V103A converts 35 bits of CMOS/TTL data,
clocked on the rising or falling edge of an input clock
(selectable), into six LVDS (Low Voltage Differential
Signaling) serial data stream pairs. In video
applications the 35 bits is normally divided into 10 bits
for each R, G and B channel and 5 control bits.
When combined with the V104 LVDS display interface
receiver, the V103A + V104 combination provides a
35-bit wide, 90 MHz transport. The rate of each LVDS
channel is 630 Mbps for a 90MHz data input clock, 945
Mbps for 135MHz.
Features
•
Pin compatible with THine THC63LVD103
•
Wide pixel clock range: 8 - 135 MHz
•
Guaranteed operation over
-20 to +85° C
ambient
temperature
•
Supports a wide range of video and graphics modes
including VGA, SVGA, XGA, SXGA, SXGA+, NTSC,
PAL, SDTV, and HDTV up to 1080I or 720P
•
Internal PLL requires no external loop filter
•
Selectable rising or falling clock edge for data
alignment
•
Compatible with Spread Spectrum clock source
•
Reduced LVDS output voltage swing mode
(selectable) to minimize EMI
•
CMOS/TTL data inputs can be configured for
reduced input voltage swing
•
•
•
•
Single 3.3 V supply
Low power consumption CMOS design
Power down mode
64-pin TQFP lead free package
Block Diagram
TA0-6
TB0-6
TC0-6
TD0-6
TE0-6
RS
R/F
/PWDN
7
7
7
7
7
TA+
TA-
TB+
TB-
Parallel
to Serial
TC+
TC-
TD+
TD-
TE+
TE-
CLKIN
(8 to 135 MHz)
PLL
TCLK+
TCLK-
V103A Datasheet
1
11/18/05
Revision 3.2
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 • t e l ( 4 0 8) 2 97 - 1 2 0 1 • w ww. i c s t . co m
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
