IC41C16105S
IC41LV16105S
.EATURES
1M x 16 (16-MBIT) DYNAMIC RAM
WITH .AST PAGE MODE
TTL compatible inputs and outputs; tristate I/O
Refresh Interval: 1,024 cycles/16 ms,
1,024 cycles / 128ms Self Refresh
Refresh Mode:
RAS-Only, CAS-before-RAS
(CBR),
Hidden, and Self Refresh
JEDEC standard pinout
Single power supply:
5V ± 10% (IC41C16105S)
3.3V ± 10% (IC41LV16105S)
Byte Write and Byte Read operation via two
CAS
Industrail temperature range -40
o
C to 85
o
C
DESCRIPTION
The
1+51
IC41C16105S and IC41LV16105S are 1,048,576 x
16-bit high-performance CMOS Dynamic Random Access
Memories. .ast Page Mode allows 1,024 random accesses
within a single row with access cycle time as short as 20 ns per
16-bit word. The Byte Write control, of upper and lower byte,
makes the IC41C16105S ideal for use in 16-, 32-bit wide data
bus systems.
These features make the IC41C16105S and IC41LV16105S
ideally suited for high-bandwidth graphics, digital signal
processing, high-performance computing systems, and
peripheral applications.
The IC41C16105S and IC41LV16105S are packaged in a
42-pin 400mil SOJ and 400mil 44- (50-) pin TSOP-2.
KEY TIMING PARAMETERS
Parameter
Max.
RAS
Access Time (t
RAC
)
Max.
CAS
Access Time (t
CAC
)
Max. Column Address Access Time (t
AA
)
Min. .ast Page Mode Cycle Time (t
PC
)
Min. Read/Write Cycle Time (t
RC
)
-50
50
13
25
20
84
-60
60
15
30
25
104
Unit
ns
ns
ns
ns
ns
PIN CON.IGURATIONS
44(50)-Pin TSOP-2
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
15
16
17
18
19
20
21
22
23
24
25
42-Pin SOJ
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
50
49
48
47
46
45
44
43
42
41
40
36
35
34
33
32
31
30
29
28
27
26
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A9
I/O0-15
WE
OE
RAS
UCAS
LCAS
Vcc
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Power
Ground
No Connection
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
DR011-0A 05/23/2001
1
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
