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IC41C16257-60TI 参数 Datasheet PDF下载

IC41C16257-60TI图片预览
型号: IC41C16257-60TI
PDF下载: 下载PDF文件 查看货源
内容描述: 256K ×16 ( 4兆位)动态RAM具有快速页面模式 [256K x 16 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE]
分类和应用: 存储内存集成电路光电二极管动态存储器
文件页数/大小: 20 页 / 762 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
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IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
256K x 16 (4-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
FEATURES
DESCRIPTION
The
ICSI
IC41C16257 and the IC41LV16257 are 262,144
Fast access and cycle time
x 16-bit high-performance CMOS Dynamic Random Access
TTL compatible inputs and outputs
Memory. Fast Page Mode allows 512 random accesses
Refresh Interval: 512 cycles/8 ms
within a single row with access cycle time as short as 12 ns
per 16-bit word. The Byte Write control, of upper and lower
Refresh Mode:
RAS-Only, CAS-before-RAS
byte, makes these devices ideal for use in 16-, 32-bit wide
(CBR), Hidden
data bus systems.
Self Refresh Mode: 512 cycles/64 ms (S version
These features make the IC41C16257 and the IC41LV16257
only)
ideally suited for high band-width graphics, digital signal
JEDEC standard pinout
processing, high-performance computing systems, and
peripheral applications.
Single power supply:
— 5V ± 10% (IC41C16257)
The IC41C16257 and the IC41LV16257 are packaged in a
40-pin, 400mil SOJ and TSOP-2.
— 3.3V ± 10% (IC41LV16257)
Byte Write and Byte Read operation via
KEY TIMING PARAMETERS
two
CAS
Parameter
-35
-50
-60 Unit
Available in 40-pin SOJ and TSOP-2
Max.
RAS
Access Time (t
RAC
)
Max.
CAS
Access Time (t
CAC
)
Max. Column Address Access Time (t
AA
)
Min. Fast Page Mode Cycle Time (t
PC
)
35
10
18
12
60
50
14
25
20
90
60
15
30
25
110
ns
ns
ns
ns
ns
PIN CONFIGURATIONS
40-Pin TSOP-2
40-Pin SOJ
Min. Read/Write Cycle Time (t
RC
)
PIN DESCRIPTIONS
A0-A8
I/O0-I/O15
WE
OE
RAS
UCAS
LCAS
Vcc
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Upper Column Address
Strobe
Lower Column Address
Strobe
Power
Ground
No Connection
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
DR021-0A 08/11/2001