IC42S16102
512K x 16 Bits x 2 Banks (16-MBIT)
SYNCHRONOUS DYNAMIC RAM
FEATURES
• Driver Strength for High capacitive bus loading
• Clock frequency: 200, 166, 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Two banks can be operated simultaneously and
independently
• Dual internal bank controlled by A11 (bank select)
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto refresh, self refresh
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable
CAS
latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
• Byte controlled by LDQM and UDQM
• Package 400mil 50-pin TSOP-2 and 60ball(16M)
VF-BGA
• Pb(lead)-free package is available
DESCRIPTION
ICSI
's 16Mb Synchronous DRAM IC42S16102 is organized
as a 524,288-word x 16-bit x 2-bank for improved
performance. The synchronous DRAMs achieve high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
PIN CONFIGURATIONS
50-Pin TSOP-2
VCC
DQ0
DQ1
GNDQ
DQ2
DQ3
VCCQ
DQ4
DQ5
GNDQ
DQ6
DQ7
VCCQ
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
GND
DQ15
DQ14
GNDQ
DQ13
DQ12
VCCQ
DQ11
DQ10
GNDQ
DQ9
DQ8
VCCQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
GND
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
DR042-0A 01/18/2005
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
