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IC42S32400-6T 参数 Datasheet PDF下载

IC42S32400-6T图片预览
型号: IC42S32400-6T
PDF下载: 下载PDF文件 查看货源
内容描述: 1M ×32位×4银行( 128兆位) SDRAM [1M x 32 Bit x 4 Banks (128-MBIT) SDRAM]
分类和应用: 动态存储器
文件页数/大小: 62 页 / 897 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
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IC42S32400
IC42S32400L
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.Table 2 shows the truth
table for the operation commands.
Table 2.Truth Table (Note (1),(2))
Command
BankActivate
BankPrecharge
PrechargeAll
Write
State
Idle
(3)
Any
Any
Active
(3)
CKEn-1 CKE
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
H
H
X
X
DQM
(6)
BS0,1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
V
V
X
V
V
V
V
A10
L
H
L
H
L
H
A11,A9-0
X
X
Column
address
(A0 ~A7)
Column
address
(A0 ~A7)
CS# RAS# CAS# WE#
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
Clock Suspend Mode Exit Active
Power Down Mode Exit
Any
(PowerDown)
Data Write/Output Enable Active
Data Mask/Output Disable Active
X
H
L
X
X
L
L
L
H
H
H
H
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
X
H
H
H
L
L
L
L
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
X
H
L
L
L
L
H
H
L
H
L
X
H
H
X
H
X
X
H
X
X
H
X
X
Row address
Write and Auto Precharge Active
(3)
Read
Read and Autoprecharge
Mode Register
No-Operation
Burst Stop
Device Deselect
AutoRefresh
SelfRefresh Entry
SelfRefresh Exit
Active
(3)
Active
(3)
Set Idle
Any
Active
(4)
Any
Idle
Idle
Idle
(SelfRefresh)
Clock Suspend Mode Entry Active
Power Down Mode Entry
Any
(5)
OP code
X
X
X
X
X
X
X
X
X
X
X
X
Note:
1. V =Valid,X =Don ’t care,L =Logic low,H =Logic high
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1,2,4,8,and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle,device state is clock suspend mode.
6. DQM0-3
6
Integrated Circuit Solution Inc.
DR038-0C 02/01/2005