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IC42S32800L-7BG 参数 Datasheet PDF下载

IC42S32800L-7BG图片预览
型号: IC42S32800L-7BG
PDF下载: 下载PDF文件 查看货源
内容描述: 2M ×32位×4银行( 256兆位) SDRAM [2M x 32 Bit x 4 Banks (256-MBIT) SDRAM]
分类和应用: 存储动态存储器
文件页数/大小: 62 页 / 857 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
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IC42S32800
IC42S32800L
3
PrechargeAll command
(RAS#=”L”,CAS#=”H”,WE#=”L”,BS =Don t care,A10 =”H”)
The PrechargeAll command precharges all the four banks simultaneously and can be issued even if all banks are
not in the active state.All banks are then switched to the idle state.
4
Read command
(RAS#=”H”,CAS#=”L”,WE#=”H”,BS =Bank,A10 =”L”,A0-A7 =Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active row in an active
bank.The bank must be active for at least tRCD(min.)before the Read command is issued.During read bursts,
the valid data-out element from the starting column address will be available following the CAS#latency after the
issue of the Read command.Each subsequent data- out element will be valid by the next positive clock edge (refer
to the following figure).The DQs go into high-impedance at the end of the burst unless other command is initiated.
The burst length,burst sequence,and CAS#latency are determined by the mode register which is already
programmed.A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and
continue).
8
Integrated Circuit Solution Inc.
DR046-0B 12/21/2004