IC61C256AH
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
-10
Symbol
Parameter
Write Cycle Time
CE
to Write End
Address Setup Time
to Write End
Address Hold
from Write End
Address Setup Time
WE
Pulse Width
Data Setup to Write End
Data Hold from Write End
WE
HIGH to Low-Z Output
Min. Max.
-12
Min. Max.
-15
Min. Max.
-20
Min. Max.
-25
Min. Max.
Unit
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
(4)
t
SD
t
HD
t
LZWE
10
9
9
0
0
8
7
0
—
0
—
—
—
—
—
—
—
—
6
—
12
10
10
0
0
8
7
0
—
0
—
—
—
—
—
—
—
—
6
—
15
10
12
0
0
10
9
0
—
0
—
—
—
—
—
—
—
—
7
—
20
13
15
0
0
13
10
0
—
0
—
—
—
—
—
—
—
—
8
—
25
15
20
0
0
15
12
0
—
0
—
—
—
—
—
—
—
—
10
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
HZWE
(2)
WE
LOW to High-Z Output
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
4. Tested with
OE
HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1
(WE Controlled)
(1,2 )
t
WC
ADDRESS
VALID ADDRESS
t
SA
CE
t
SCE
t
HA
WE
t
AW
t
PWE1
t
PWE2
t
HZWE
t
LZWE
HIGH-Z
D
OUT
DATA UNDEFINED
t
SD
D
IN
t
HD
DATA
IN
VALID
Integrated Circuit Solution Inc.
AHSR010-0D 4/19/2002
7
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
