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IC62C1024AL-70T 参数 Datasheet PDF下载

IC62C1024AL-70T图片预览
型号: IC62C1024AL-70T
PDF下载: 下载PDF文件 查看货源
内容描述: 128K ×8低功耗CMOS SRAM [128K x 8 Low Power CMOS SRAM]
分类和应用: 静态存储器
文件页数/大小: 9 页 / 142 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
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IC62C1024AL
WRITE CYCLE NO. 2 (CE1 CE2 Controlled)
(1,2)
CE1,
CE1
t
WC
ADDRESS
t
SA
t
SCE1
t
HA
CE1
t
SCE2
CE2
t
AW
t
PWE
(4)
WE
t
HZWE
t
LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
SD
t
HD
DIN
DATA-IN VALID
Notes:
1. The internal write time is defined by the overlap of
CE1
LOW, CE2 HIGH and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if
OE
= V
IH
.
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Vcc for Data Retention
Data Retention Current
Data Retention Setup Time
Recovery Time
Test Condition
See Data Retention Waveform
Vcc = 3.0V,
CE1
> Vcc – 0.2V
See Data Retention Waveform
See Data Retention Waveform
Com.
Ind.
Min.
2.0
0
Max.
5.5
250
400
Unit
V
µA
ns
ns
V
DR
I
DR
t
SDR
t
RDR
t
RC
DATA RETENTION WAVEFORM (CE1 Controlled)
CE1
t
SDR
V
CC
Data Retention Mode
t
RDR
5.0V
3.0V
V
DR
CE1
V
CC
- 0.2V
CE1
GND
8
Integrated Circuit Solution Inc.
ALSR009-0A 5/7/2002