IC62LV12816L
IC62LV12816LL
IC62LV12816L
IC62LV12816LL
128K x 16 LOW VOLTAGE, ULTRA
LOW POWER CMOS STATIC RAM
.EATURES
High-speed access times: 55, 70, 100 ns
CMOS low power operation
-- 60 mW (typical) operating
-- 3 µW (typical) CMOS standby
TTL compatible interface levels
Single 2.7V-3.6V Vcc power supply
.ully static operation: no clock or refresh re-
quired
Three state outputs
Data control for upper and lower bytes
Industrial temperature available
Available in the 44-pin TSOP-2 and 48-pin
6*8mm T.-BGA
DESCRIPTION
The
1+51
IC62LV12816L and IC62LV12816LL are high-speed,
2.097,152-bit static RAMs organized as 131,072 words by 16
bits. They are fabricated using
1+51
's high-performance CMOS
technology. This highly reliable process coupled with innova-
tive circuit design techniques, yields high-performance and
low power consumption devices.
When
CE
is HIGH (deselected) or when
CE
is low and both
LB
and
UB
are HIGH, the device assumes a standby mode at
which the power dissipation can be reduced by using CMOS
input levels.
Easy memory expansion is provided by using Chip Enable
Output and Enable inputs,
CE
and
OE.
The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IC62LV12816L and IC62LV12816LL are packaged in the
JEDEC standare 44-pin 400mil TSOP-2 and 48-pin 6*8mm
T.-BGA.
.UNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K x 16
MEMORY ARRAY
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
LPSR011-0B 06/06/2001
1
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
