IC62LV25616L
IC62LV25616LL
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
-55
Symbol
Parameter
Write Cycle Time
CE
to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
LB, UB
Valid to End of Write
WE
Pulse Width
Data Setup to Write End
Data Hold from Write End
Min.
55
50
50
0
0
45
40
25
0
—
5
Max.
—
—
—
—
—
—
—
—
—
30
—
Min.
70
65
65
0
0
60
40
30
0
—
5
-70
Max.
—
—
—
—
—
—
—
—
—
30
—
-100
Min. Max
100
80
80
0
0
80
80
40
0
—
5
—
—
—
—
—
—
—
—
—
40
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWB
t
PWE
t
SD
t
HD
t
HZWE
(3)
WE
LOW to High-Z Output
t
LZWE
(3)
WE
HIGH to Low-Z Output
Notes:
1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 2.2V and output loading specified in
Figure 1.
2. The internal write time is defined by the overlap of
CE
LOW, and
UB
or
LB,
and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1
(1,2)
(
CE
Controlled
)
t
WC
ADDRESS
VALID ADDRESS
t
SA
CE
t
SCS
t
HA
t
AW
t
PWE
WE
t
PBW
UB, LB
t
HZWE
D
OUT
DATA UNDEFINED
HIGH-Z
t
LZWE
t
SD
D
IN
t
HD
DATA
IN
VALID
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the
CE
and
WE
inputs and at least
one of the
LB
and
UB
inputs being in the LOW state.
2. WRITE = (CE) [ (
LB
) = (UB) ] (WE).
8
Integrated Circuit Solution Inc.
LPSR013-0D 10/11/2002
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
