IC62LV256L
WRITE CYCLE NO. 2 (CE Controlled)
(1,2)
CE
t
WC
ADDRESS
t
SA
t
SCE
t
HA
CE
t
AW
t
PWE
WE
t
HZWE
t
LZWE
HIGH-Z
D
OUT
DATA UNDEFINED
t
SD
t
HD
D
IN
DATA-IN VALID
Notes:
1. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if
OE
≥
V
IH
.
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns)
15
20
25
Order Part No.
IC62LV256L-15T
IC62LV256L-15J
IC62LV256L-20T
IC62LV256L-20J
IC62LV256L-25T
IC62LV256L-25J
Package
8*13.4mm TSOP-1
300mil SOJ
8*13.4mm TSOP-1
300mil SOJ
8*13.4mm TSOP-1
300mil SOJ
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns)
15
20
25
Order Part No.
IC62LV256L-15TI
IC62LV256L-15JI
IC62LV256L-20TI
IC62LV256L-20JI
IC62LV256L-25TI
IC62LV256L-25JI
Package
8*13.4mm TSOP-1
300mil SOJ
8*13.4mm TSOP-1
300mil SOJ
8*13.4mm TSOP-1
300mil SOJ
8
Integrated Circuit Solution Inc.
ALSR008-0A 10/5/2001
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
