IC62LV256-70JI 参数 Datasheet PDF下载

IC62LV256

WRITE CYCLE NO. 2 (CE Controlled)

(1,2)

CE

t

WC

ADDRESS

t

SA

t

SCE

t

HA

CE

t

AW

t

PWE

WE

t

HZWE

t

LZWE

HIGH-Z

D

OUT

DATA UNDEFINED

t

SD

t

HD

D

IN

DATA-IN VALID

Notes:

1. The internal write time is defined by the overlap of

CE

LOW and

WE

LOW. All signals must be in valid states to initiate a Write,

but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling

edge of the signal that terminates the Write.

2. I/O will assume the High-Z state if

OE

≥

V

IH

.

8

Integrated Circuit Solution Inc.

ALSR007-0A 10/5/2001