IC62LV5128L
IC62LV5128LL
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range, Standard and Low Power)
-55
Symbol
Parameter
Write Cycle Time
CE
to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
WE
Pulse Width
Data Setup to Write End
Data Hold from Write End
WE
LOW to High-Z Output
WE
HIGH to Low-Z Output
Min.
55
50
50
0
0
40
25
0
—
5
Max.
—
—
—
—
—
—
—
—
30
—
Min.
70
65
65
0
0
40
30
0
—
5
-70
Max.
—
—
—
—
—
—
—
—
30
—
-100
Min. Max
100
80
80
0
0
80
40
0
—
5
—
—
—
—
—
—
—
—
40
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
(3)
t
LZWE
(3)
Notes:
1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 2.2V and output loading specified in
Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
AC WAVEFORMS
WRITE CYCLE NO. 1
(
CE
Controlled
)
t
WC
ADDRESS
t
SCE
t
HA
CE
t
AW
WE
t
SA
t
HZWE
t
PWE
t
LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
SD
t
HD
DIN
DATA-IN VALID
8
Integrated Circuit Solution Inc.
LPSR012-0B 08/31/2001
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
