Integrated
Circuit
Systems, Inc.
ICS843003
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
F
EATURES
• Three 3.3V LVPECL outputs on two banks, A Bank with
one LVPECL pair and B Bank with 2 LVPECL output pairs
• Using a 31.25MHz or 26.041666 crystal, the two output
banks can be independently set for 625MHz, 312.5MHz,
156.25MHz or 125MHz
• Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
• VCO range: 560MHz to 700MHz
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):
0.51ps (typical)
• RMS phase noise at 156.25MHz
Phase noise:
Offset
Noise Power
100Hz ............... -96.8 dBc/Hz
1KHz .............. -119.1 dBc/Hz
10KHz .............. -126.4 dBc/Hz
100KHz .............. -127.0 dBc/Hz
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Industrial temperature available upon request
G
ENERAL
D
ESCRIPTION
The ICS843003 is a 3 differential output LVPECL
Synthesizer designed to generate Ethernet refer-
HiPerClockS™
ence clock frequencies and is a member of the
HiPerClocks™ family of high performance clock
solutions from ICS. Using a 31.25MHz or
26.041666MHz, 18pF parallel resonant crystal, the following fre-
quencies can be generated based on the settings of 4 frequency
select pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]): 625MHz,
312.5MHz, 156.25MHz, and 125MHz. The 843003 has 2 output
banks, Bank A with 1 differential LVPECL output pair and Bank
B with 2 differential LVPECL output pairs.
ICS
The two banks have their own dedicated frequency select pins
and can be independently set for the frequencies mentioned
above. The ICS843003 uses ICS’ 3rd generation low phase noise
VCO technology and can achieve 1ps or lower typical rms phase
jitter, easily meeting Ethernet jitter requirements. The ICS843003
is packaged in a small 24-pin TSSOP package.
P
IN
A
SSIGNMENT
DIV_SELB0
VCO_SEL
MR
V
CCO
_
A
QA0
nQA0
OEB
OEA
FB_DIV
V
CCA
V
CC
DIV_SELA0
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DIV_SELB1
V
CCO
_
B
QB0
nQB0
QB1
nQB1
XTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
V
EE
DIV_SELA1
B
LOCK
D
IAGRAM
OEA
Pullup
DIV_SELA[1:0]
VCO_SEL
Pullup
ICS843003
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
QA0
Top View
nQA0
TEST_CLK
Pulldown
0
00
01
0
10
11
÷1
÷2
(default)
÷4
÷5
XTAL_IN
OSC
XTAL_OUT
XTAL_SEL
Pullup
1
Phase
Detector
VCO
625MHz
1
QB0
FB_DIV
0 = ÷20 (default)
1 = ÷24
00
01
10
11
÷1
÷2
÷4
(default)
÷5
nQB0
QB1
nQB1
FB_DIV
Pulldown
DIV_SELB[1:0]
MR
Pulldown
OEB
Pullup
843003AG
www.icst.com/products/hiperclocks.html
1
REV. A JULY 27, 2004
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
