ICS8442
Integrated
Circuit
Systems, Inc.
700MH
Z
, CRYSTAL
O
SCILLATOR
-
TO-DIFFERENTIAL
LVDS FREQUENCY
SYNTHESIZER
The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
traces should be routed first and should be locked prior to routing
other signal traces.
• The traces with 50Ω transmission lines TL1 andTL2 at
FOUT and nFOUT should have equal delay and run ad-
jacent to each other.Avoid sharp angles on the clock trace.
Sharp angle turns cause the characteristic impedance to
change on the transmission lines.
POWER AND GROUNDING
Place the decoupling capacitors C14 and C15 as close as pos-
sible to the power pins. If space allows, placing the decoupling
capacitor at the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin generated by the via.
• Keep the clock trace on same layer.Whenever possible,
avoid any vias on the clock traces. Any via on the trace
can affect the trace characteristic impedance and hence
degrade signal quality.
Maximize the pad size of the power (ground) at the decoupling
capacitor.Maximize the number of vias between power (ground)
and the pads.This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
If VDDA shares the same power supply with VDD, insert the RC
filter R7, C11, and C16 in between. Place this RC filter as close
to the VDDA as possible.
• Make sure no other signal trace is routed between the
clock trace pair.
CLOCK TRACES AND TERMINATION
The matching termination resistors R1 and R2 should be located
as close to the receiver input pins as possible. Other termination
scheme can also be used but is not shown in this example.
The component placements, locations and orientations should
be arranged to achieve the best clock signal quality. Poor clock
signal quality can degrade the system performance or cause
system failure. In the synchronous high-speed digital system,
the clock signal is less tolerable to poor signal quality than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The trace shape and the trace
delay might be restricted by the available space on the board and
the component location.While routing the traces, the clock signal
CRYSTAL
The crystal X1 should be located as close as possible to the pins
24 (XTAL1) and 25 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
GND
C1
C2
VDD
X1
VIA
U1
PIN 1
C16
C11
VDDA
R7
Close to the input
pins of the
receiver
For FOUT0/n FOUT0
output TL1, TL1N are
50 Ohm traces and
equal length
C14
TL1
R1
Same requirement fo
FOUT1/nFOUT1
C15
TL1N
FIGURE 5B. PCB BOARD LAYOUT FOR ICS8442
8442AY
www.icst.com/products/hiperclocks.html
REV. C JULY 8, 2004
11
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
