IS41C16256
IS41LV16256
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
I
IL
I
IO
V
OH
V
OL
I
CC
1
Parameter
Input Leakage Current
Output Leakage Current
Output High Voltage Level
Output Low Voltage Level
Standby Current: TTL
Test Condition
Any input 0V < V
IN
< Vcc
Other inputs not under test = 0V
Output is disabled (Hi-Z)
0V < V
OUT
< Vcc
I
OH
= –2.5 mA
I
OL
=+2.1mA
RAS, LCAS, UCAS
> V
IH
Commerical 5V
Industrial
5V
Commerical 3.3V
Industrial
3.3V
RAS, LCAS, UCAS
> V
CC
– 0.2V
5V
3.3V
-25
-35
-50
-60
-25
-35
-50
-60
-25
-35
-50
-60
-25
-35
-50
-60
Speed
Min.
–10
–10
2.4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
10
10
—
0.4
2
3
1
2
1
0.5
260
230
180
170
250
220
170
160
260
230
180
170
260
230
180
170
Unit
µA
µA
V
V
mA
I
CC
2
I
CC
3
Standby Current: CMOS
mA
mA
Operating Current:
RAS, LCAS, UCAS,
(2,3,4)
Random Read/Write
Address Cycling, t
RC
= t
RC
(min.)
Average Power Supply Current
Operating Current:
RAS
= V
IL
,
LCAS, UCAS,
(2,3,4)
EDO Page Mode
Cycling t
PC
= t
PC
(min.)
Average Power Supply Current
Refresh Current:
RAS
Cycling,
LCAS, UCAS
> V
IH
(2,3)
RAS-Only
t
RC
= t
RC
(min.)
Average Power Supply Current
Refresh Current:
RAS, LCAS, UCAS
Cycling
(2,3,5)
CBR
t
RC
= t
RC
(min.)
Average Power Supply Current
I
CC
4
mA
I
CC
5
mA
I
CC
6
mA
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight
RAS
refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight
RAS
cycles wake-up should be repeated any time the t
REF
refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
6
Integrated Circuit Solution Inc.
DR001-0E 01/25/2002
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
