IS41C16100S
IS41LV16100S
1M x 16 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
FEATURES
• Extended Data-Out (EDO) Page Mode access cycle
• TTL compatible inputs and outputs; tristate I/O
• Refresh Interval:
Refresh Mode:
1,024 cycles /16 ms
RAS-Only, CAS-before-RAS
(CBR), and Hidden
Self refresh Mode
- 1,024 cycles / 128ms
• JEDEC standard pinout
• Single power supply:
5V ± 10% (IS41C16100S)
3.3V ± 10% (IS41LV16100S)
• Byte Write and Byte Read operation via two
CAS
• Industrail Temperature Range -40°C to 85°C
The IS41C16100S and IS41LV16100S are packaged in a
42-pin 400mil SOJ and 400mil 50- (44-) pin TSOP-2.
DESCRIPTION
The
ICSI
IS41C16100S and IS41LV16100S are 1,048,576 x
16-bit high-performance CMOS Dynamic Random Access
Memories. These devices offer an accelerated cycle access
called EDO Page Mode. EDO Page Mode allows 1,024 ran-
dom accesses within a single row with access cycle time as
short as 20 ns per 16-bit word. The Byte Write control, of upper
and lower byte, makes the IS41C16100S ideal for use in
16-, 32-bit wide data bus systems.
These features make the IS41C16100Sand IS41LV16100S
ideally suited for high-bandwidth graphics, digital signal
processing, high-performance computing systems, and
peripheral applications.
EY TIMING PARAMETERS
Parameter
Max.
RAS
Access Time (t
RAC
)
Max.
CAS
Access Time (t
CAC
)
Max. Column Address Access Time (t
AA
)
Min. EDO Page Mode Cycle Time (t
PC
)
Min. Read/Write Cycle Time (t
RC
)
-45
(1)
45
11
22
16
77
-50
50
13
25
20
84
-60
60
15
30
25
104
Unit
ns
ns
ns
ns
ns
Note:
1. 45 ns Only for Vcc = 3.3V.
PIN CONFIGURATIONS
50(44)-Pin TSOP II
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
36
35
34
33
32
31
30
29
28
27
26
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
42-Pin SOJ
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A9
I/O0-15
WE
OE
RAS
UCAS
LCAS
Vcc
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Power
Ground
No Connection
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
DR004-0B
1
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
