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IS42S32400A-10T 参数 Datasheet PDF下载

IS42S32400A-10T图片预览
型号: IS42S32400A-10T
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆×8 , 8Meg X16和4Meg ×32 128兆位同步DRAM [16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM]
分类和应用: 动态存储器
文件页数/大小: 66 页 / 553 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
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IS42S81600A, IS42LS81600A
IS42S16800A, IS42LS16800A
IS42S32400A, IS42LS32400A
16Meg x 8, 8Meg x16 & 4Meg x 32
128-MBIT SYNCHRONOUS DRAM
FEATURES
• Clock frequency: 133 100, MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Power supply
IS42LS81600A
IS42LS16800A
IS42LS32400A
IS42S81600A
IS42S16800A
IS42S32400A
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Extended Mode Register
• Programmable Power Reduction Feature by
partial array activation during Self-Refresh
• Auto Refresh (CBR)
• Temp. Compensated Self Refresh.
• Self Refresh with programmable refresh periods
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable
CAS
latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
• Industrial Temperature Availability
V
DDQ
V
DD
2.5V 1.8V (2.5V tolerant)
2.5V 1.8V (2.5V tolerant)
2.5V 1.8V (2.5V tolerant)
3.3V 3.3V
3.3V 3.3V
3.3V 3.3V
IS42LS81600A
IS42S81600A
4M x8x4 Banks
54pin TSOPII
ISSI
®
ADVANCED INFORMATION
AUGUST 2002
OVERVIEW
ISSI
's 128Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock
input.The 128Mb SDARM is organized as follows.
IS42LS16800A
IS42S16800A
2M x16x4 Banks
54ball FBGA
54 pin TSOPII
IS42LS32400A
IS42S32400A
2M x16x4 Banks
90ball FBGA
86pin TSOPII
KEY TIMING PARAMETERS
Parameter
Clk Cycle Time
CAS
Latency = 3
CAS
Latency = 2
Clk Frequency
CAS
Latency = 3
CAS
Latency = 2
Access Time from Clock
CAS
Latency = 3
CAS
Latency = 2
Row to Column Delay Time (t
RCD
)
Row Precharge Tim (t
RP
)
-7
7
10
133
100
5.4
6
15
15
-10
10
10
100
100
7
9
18
18
Unit
ns
ns
Mhz
Mhz
ns
ns
ns
ns
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
ADVANCED INFORMATION, Rev. 00A
08/01/02
1