IS61LV12816
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
Symbol
Parameter
Write Cycle Time
CE
to Write End
Address Setup Time
to Write End
Address Hold from Write End
Address Setup Time
LB, UB
Valid to End of Write
WE
Pulse Width
Data Setup to Write End
Data Hold from Write End
Min.
8
7
7
0
0
7
7
4.5
0
0
-8
Max.
3
-10
Min. Max.
10
8
8
0
0
8
8
5
0
0
4
-12
Min. Max.
12
8
8
0
0
9
9
6
0
0
5
-15
Min. Max.
15
10
10
0
0
10
10
7
0
0
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWB
t
PWE
"
t
SD
t
HD
!
"
#
$
%
&
'
t
HZWE
WE
LOW to High-Z Output
t
LZWE
WE
HIGH to Low-Z Output
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE
LOW and
UB
or
LB,
and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
4.Tested with
OE
Hith.
Integrated Circuit Solution, Inc.
SR023_0C
7
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
