IS61LV5128
WRITE CYCLE NO. 2
(1,2)
(WE Controlled,
OE
is HIGH During Write Cycle)
t
WC
ADDRESS
VALID ADDRESS
t
HA
OE
CE
LOW
t
AW
t
PWE1
WE
t
SA
D
OUT
DATA UNDEFINED
t
HZWE
HIGH-Z
t
LZWE
t
SD
D
IN
t
HD
DATA
IN
VALID
WRITE CYCLE NO. 3
(WE Controlled,
OE
is LOW During Write Cycle)
t
WC
ADDRESS
VALID ADDRESS
OE
CE
LOW
t
HA
LOW
t
AW
t
PWE2
WE
t
SA
D
OUT
DATA UNDEFINED
t
HZWE
HIGH-Z
t
LZWE
t
SD
D
IN
t
HD
DATA
IN
VALID
Notes:
1. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if
OE
> V
IH
.
Integrated Circuit Solution, Inc.
SR027-0C
7
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
