IS62C1024-45WI 参数 Datasheet PDF下载

IS62C1024

WRITE CYCLE NO. 2 (CE1 CE2 Controlled)

(1,2)

CE1,

CE1

t

WC

ADDRESS

VALID ADDRESS

t

HA

OE

CE

LOW

t

AW

t

PWE1

WE

t

SA

D

OUT

DATA UNDEFINED

t

HZWE

HIGH-Z

t

LZWE

t

SD

D

IN

t

HD

DATA

IN

VALID

Notes:

1. The internal write time is defined by the overlap of

CE1

LOW, CE2 HIGH and

WE

LOW. All signals must be in valid states to

initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the

rising or falling edge of the signal that terminates the Write.

2. I/O will assume the High-Z state if

OE

= V

IH

.

Integrated Circuit Solution Inc.

SR016-0B

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