IS62LV1024L/LL
WRITE CYCLE NO. 2 (+- CE2 Controlled)
(1,2)
+- ,
+-
t
WC
ADDRESS
t
SA
t
SCE1
t
HA
CE1
t
SCE2
CE2
t
AW
t
PWE
(4)
WE
t
HZWE
t
LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
SD
t
HD
DIN
DATA-IN VALID
Notes:
1. The internal write time is defined by the overlap of
CE1
LOW, CE2 HIGH and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if
OE
= V
IH
.
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Vcc for Data Retention
Data Retention Current
Test Condition
See Data Retention Waveform
Vcc = 2.0V,
CE1
≥
Vcc 0.2V
Com. (-L)
Com. (-LL)
Ind. (-L)
Ind. (-LL)
Min.
2.0
0
Max.
3.6
30
5
50
10
Unit
V
µA
µA
µA
µA
ns
ns
V
DR
I
DR
t
SDR
t
RDR
Data Retention Setup Time
Recovery Time
See Data Retention Waveform
See Data Retention Waveform
t
RC
DATA RETENTION WAVE.ORM (+- Controlled)
+-
t
SDR
V
CC
Data Retention Mode
t
RDR
3.0V
2.2V
V
DR
CE1
≥
V
CC
- 0.2V
CE1
GND
8
Integrated Circuit Solution Inc.
LPSR018-0D 07/06/2001
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
